QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 15)

1. In the IP Catalog, double-click pattern_checker_system from the System group.

2. In the parameter editor, click Finish to accept the default settings.

3. Rename the instance to pattern_checker_subsystem.

4. Set the pattern_checker_subsystem clk to clk_0.

5. Connect the pattern_checker_subsystem slave interface to the mm_bridge m0 interface.

6. Connect the pattern_checker_subsystem reset interface to the clk_0 clk_reset interface.

Add Memory Master Components

Memory masters access the SDRAM controller by writing the test pattern to the memory and reading the

pattern back for validation. The RAM test controller accepts commands from the processor and controls

the memory masters. Each command contains a start address, test length in bytes, and memory block size

in bytes. The RAM test controller segments the commands into smaller block transfers and issues the

commands to the read and write masters independently via streaming connections.

When the pattern reader or writer components complete a block transfer, they signal to the RAM test

controller that they are ready for another command. The RAM test controller issues the block-sized

commands independently, which minimizes the number of idle cycles between memory transfers. The

RAM test controller also ensures that the pattern reader never overtakes the pattern writer with respect to

the memory locations it is testing, otherwise data corruption occurs.

The SDRAM controller is parameterized to use a local maximum burst length of 2. The pattern reader and

writer components are also configured to match this burst length to maximize the memory bandwidth.

Add a Pattern Writer Component

The pattern writer component accepts memory transfer commands from the RAM test controller with the

command streaming interface. The st_data streaming interface accepts data provided by the design’s

pattern generator. The mm_data memory-mapped interface writes the pattern data to the SDRAM

controller.

Before you begin

1. In the IP Catalog, double-click Pattern Writer from the Memory Test Microcores group.

2. In the parameter editor, turn on Burst Enable.

3. Ensure that the Maximum Burst Count is 2.

4. Ensure that Enable Burst Re-alignment is turned on.

5. To accept the other default parameters, click Finish.

6. Rename the instance to pattern_writer.

7. Set the pattern_writer clock to clk_0.

8. Connect the pattern_writer st_data interface to the pattern_generator_subsystem st_data_out

interface.

9. Export the pattern_writer mm_data interface with the name write_master.

Add a Pattern Reader Component

The pattern reader component accepts memory transfer commands from the RAM test controller with

the command streaming interface. The mm_data interface reads the pattern data from the SDRAM

controller. The st_data interface sends the data read from memory to the design’s pattern checker.

TU-01006

2015.05.04

Add Memory Master Components

Qsys System Design Tutorial

Altera Corporation

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