QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 2)

In this tutorial, you instantiate the complete memory tester system in the top-level system along with the

processor IP Cores, which are grouped as their own processor system, and the SDRAM Controller IP. The

Nios II processor includes a software program to control the memory tester system, which communicates

with the SDRAM Controller to access the off-chip SDRAM device under test.

Figure 1: Qsys Memory Tester

The components in the memory tester system are grouped into a single Qsys system with three major

design functions. The design hierarchy allows you to instantiate the data pattern generator and data

pattern checker components into separate systems. You can then add the memory tester system with the

memory master and controller components.

Top-Level Qsys System

Memory Tester

Data Pattern Generator Memory Master and Controller

Data Pattern Checker

Processor

IP Cores

SDRAM

Controller

SDRAM

Under Test

Custom

Pattern

Generator

PRBS

Generator

Pattern

Select

(

MUX

)

Pattern Writer

Checker

Select

(

DEMUX

)

Test Controller

PRBS

Checker

Custom

Pattern

Checker

Nios II

Onchip

RAM

(

Code

and Data

)

Avalon-MM Interface

Avalon-ST Interface

Pattern Reader

Pipeline

Bridge

JTAG

UART

Related Information

Download and Install the Tutorial Design Files on page 3

AN320: OpenCore Plus Evaluation of Megafunctions

Qsys System Design Tutorial

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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