QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 20)

Related Information

Download and Install the Tutorial Design Files on page 3

Debugging Your Design

If the memory test starts but does not complete successfully, the terminal displays failure messages. If you

see failure messages from the memory test, review the previous sections and check that you have

completed all of the instructions in this tutorial successfully. A missed connection or incorrect memory

address assignment may cause the tester design to fail on the board.

Altera provides completed systems, so that you can verify your system designs. You can copy the

completed systems into the project directory with different names, so that you can open two different

instances of Qsys for a side-by-side comparison. Alternatively, you can replace your systems with the

provided completed systems to run the memory tester design successfully.

Related Information

Download and Install the Tutorial Design Files on page 3

Verifying Hardware in System Console

You can use the Quartus II System Console to verify your system design. The design example files include

scripts that exercise your system using System Console Tcl commands. The example uses a JTAG-to-

Avalon Master Bridge component to drive the slave components, instead of a Nios II processor system.

The \quartus_ii_projects_for_boards\<development_board>\system_console directory contains the

run_sweep.tcl, base_address.tcl, and test_cases.tcl scripts. You use these scripts to set up and run

memory tests on the development board projects. You can view the scripts to help you understand the

System Console commands that drive the slave component registers. The scripts work with any board, if

you keep the same Qsys system structure.

The run_sweep.tcl file is the main script, which calls the other two scripts. The base_address.tcl file includes

information about the base addresses of the slave components from the previous chapters. If you change

the base addresses of the slave components, you must also change the addresses in the base_address.tcl file.

The test_cases.tcl file includes settings for memory span, memory block sizes, and memory block trail

distance.

The run_sweep.tcl file contains Tcl commands for the following actions:

• Initialize the components

• Adjust test parameters

• Start the PRBS pattern checker, PRBS pattern generator, and RAM controller

• Continuously poll the stop and fail bits in the PRBS checker

Related Information

Download and Install the Tutorial Design Files on page 3

Open the Tutorial Project

You can use completed design files in the tt_qsys_design\quartus_ii_projects_for_boards\<development_board>

directory.

Debugging Your Design

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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QSC Q-SYS PS-1650G Bedienungsanleitung Seite 20