QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 8)

7. Connect the two_to_one_st_mux csr interface to the mm_bridge m0 interface.

8. Export the two_to_one_st_mux st_output interface with the name st_data_out.

9. Assign the two_to_one_st_mux csr interface to a base address of 0x0440, which is a base address

higher than the end address of the prbs_pattern_generator csr interface at base address 0x0420

The output of the two-to-one streaming multiplexer carries the pattern data from either the custom

pattern generator or the PRBS pattern generator, to the pattern writer. The data, from the output of the

two-to-one streaming multiplexer, achieves a throughput of one word per clock cycle.

Verify the Memory Address Map

You control the system by accessing the memory locations allocated to each component within the

subsystem. To ensure that the memory map of the system you create matches the memory map of other

components, you must verify the base addresses for the data pattern generator system.

On the Address Map tab, verify that the entries in the Address Map table match the values in

#mwh1411073373020/table_54ED964DACCD4D7480A621FF0B0D0E00. Red exclamation marks

indicate that the address ranges overlap. Correct the base addresses, as appropriate, to ensure there are no

overlapping addresses, and your map matches this tutorial’s guidelines.

Table 1: Address Map Table

Component Address

custom_pattern_generator.csr 0x00000400 – 0x0000040f

custom_pattern_generator.pattern_access 0x00000000 – 0x000003ff

prbs_pattern_generator.csr 0x00000420 – 0x0000043f

two_to_one_st_mux.csr 0x00000440 – 0x00000447

Connect the Reset Signals

You must connect all the reset signals, which eliminates the error messages in the Messages tab. Qsys

allows multiple reset domains, or one reset signal for the system. In the design, you want to connect all the

reset signals with the incoming reset signal. To connect all the reset signals, on the System menu, select

Create Global Reset Network.

At this point in the system design, Qsys shows no remaining error messages. If you have any error

messages in the Messages tab, review the procedures to create this system to ensure you did not miss a

step. You can view the reset connections and the timing adapters on the System Contents tab, and by

selecting Show System With Qsys Interconnect on the System menu.

Save the System

At this point, there should be no remaining error messages in the Messages tab, and the system is

complete. Save the system.

Create a Data Pattern Checker Qsys System

The data pattern checker system receives a pattern from SDRAM and verifies it against the pattern from

the data pattern generator. The pattern reader sends the data to a one-to-two streaming demultiplexer

that routes the data to either the custom pattern checker or the PRBS pattern checker. The one-to-two

Verify the Memory Address Map

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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QSC Q-SYS PS-1650G Bedienungsanleitung Seite 8