QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 4)

• Detailed Diagram of the Memory Tester System

Open the Tutorial Project

The design files for the Qsys tutorial provide the custom IP design blocks that you need, and a partially

completed Quartus II project and Qsys system.

The following design requirements are included in the Qsys tutorial design files:

• Quartus II project I/O pin assignments and Synopsys Design Constraint (.sdc) timing assignments for

each supported development board.

• Parameterized Nios II processor core and software to communicate with the host PC that controls the

memory test system that you develop.

• Parameterized DDR SDRAM controller to use the memory on the development board.

To open the tutorial project:

1. Open the Quartus II software.

2. To open the Quartus II Project File (.qpf) for your board, click File > Open Project.

3. Browse to the tt_qsys_design\quartus_ii_projects_for_boards\<development_board>\ directory.

4. Select the relevant board-specific .qpf file, and then click Open.

Creating Qsys Systems

The data pattern generator and data pattern checker are design blocks for the memory tester system. In

this tutorial, you learn to instantiate, parameterize, and connect components by creating the data pattern

generator and data pattern checker Qsys systems.

• Data pattern generator—The data pattern generator generates high-speed streaming data, which

performs either as a PRBS, or as a soft programmable sequence, for example, “walking ones.” The

design sends the data with an Avalon-Streaming (Avalon-ST) connection to the pattern writer of the

memory master and control logic. The data pattern generator writes the data to memory based on

commands issued by the controller logic. When the design writes the data to memory, the pattern

reader logic reads the contents back and sends it to the data pattern verification logic.

• Data pattern checker—The data pattern checker accepts the data read back by the pattern reader from

an Avalon-ST connection. The design verifies the data pattern to ensure that the pattern it writes to

memory is identical to the data that it reads back.

Create a Data Pattern Generator Qsys System

The data pattern generator includes two components to generate test patterns, and a third component to

multiplex the data that a processor controls. You configure the pattern generator to match the width of

the memory interface. Because the data pattern generator provides a full word of data every clock cycle,

configuring the components to match the memory width provides sufficient bandwidth to access the

memory.

Note:

As you add components and make connections in your Qsys system, error and warning messages

appear in the Qsys Messages tab, indicating steps that you must perform before the system is

complete. Some error messages appear between steps and are not resolved immediately; as you

progress through the tutorial, errors are resolved, and the error messages disappear.

Open the Tutorial Project

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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