QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 24)

1. In Qsys, open the testbench system, pattern_generator_tb.qsys, from the simulation_tutorial\pattern_

generator\testbench directory.

2. On the System Contents tab, rename the instance as they appear in Table 5–1.

Qsys-Generated Components' Names New Instance Name

pattern_generator_inst DUT

pattern_generator_inst_pg_clock_bfm clock_source

pattern_generator_inst_pg_reset_bfm reset_source

pattern_generator_inst_pg_csr_bfm csr_master

pattern_generator_inst_pg_pattern_access_bfm pattern_master

pattern_generator_inst_pg_pattern_output_bfm pattern_sink

3. Double-click a BFM component to open the parameter editor and view its settings. These BFM

components are available in the Avalon Verification Suite group in the library. If necessary, you can

change the parameters for the BFMs to ensure adequate test coverage for your design.

The Qsys-generated testbench matches inserted BFMs with the exported interfaces from the design

that they drive. The test program that provides stimulus to the BFMs must account for the matching

interface. For example, an exported Avalon-MM slave interface (which expects word-aligned

addresses) is connected to an Avalon master BFM, which expects and transacts word-aligned addresses

instead of the byte or symbol addresses that are default for Avalon masters.

4. Click Cancel to close the parameter editor without making changes.

5. In the Generation dialog box, under Simulation, for Create simulation model, select Verilog.

6. Under Testbench System, select None for Create testbench Qsys system and Create testbench

simulation model.

7. Under Synthesis, select None for Create HDL design files for synthesis, and turn off Create Block

design files (.bsf).

8. Save the system.

9. Click Generate.

10.After Qsys generates the testbench, click Close.

Qsys generates the testbench system’s simulation models in the \simulation_tutorial\pattern_generator

\testbench\pattern_generator_tb\simulation directory.

Qsys generates the simulation models and a ModelSim simulation script (msim_setup.tcl), which

compiles the required files for simulation and sets up commands to load the simulation in the ModelSim

simulator. You can run this ModelSim script in ModelSim-Altera to compile, elaborate, or load for

simulation.

In this tutorial, there is an external test program to provide simulation stimulus. The tutorial design files

include a simulation script, load_sim.tcl that compiles the top-level simulation file and test program, and

calls the Qsys-generated script to compile the required files.

Run Simulation In the ModelSim-Altera Software

You can run a simulation in the ModelSim-Altera software on the testbench that you created. To

complete this simulation you use the test program provided in the design files. The test begins by writing

a walking ones pattern to the design under test.

Run Simulation In the ModelSim-Altera Software

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

Send Feedback

1 2 ... 19 20 21 22 23 24 25 26 27

Kommentare zu diesen Handbüchern

Keine Kommentare

QSC Q-SYS PS-1650G Bedienungsanleitung Seite 24

Kommentare zu diesen Handbüchern