QSC Q-SYS PS-1650G Bedienungsanleitung PDF herunterladen (Seite 19)

5. In the Quartus II software, on the Project menu, click Add/Remove Files in Project and verify that the

newly-generated .qip file, top_system.qip, and the timing constraints file, my_constraints.sdc appear

in the Files list.

6. Click Processing > Start Compilation. When compilation completes, click OK.

7. Connect the development board to a supported programming cable.

8. Click Tools > Nios II Command Shell [gcc4].

9. Type the following command to emulate your local c:/ drive for your Windows environment: cd /

cygdrive/c/.

10.Navigate to the quartus_ii_projects_for_boards\<development_board>\software directory.

11.Type the following command at the Nios II command Shell: ./batch_script.sh.

The batch script compiles the Nios II software and downloads the SRAM Object File (.sof) program‐

ming file to the FPGA.

The terminal window shows messages indicating the progress. If you see error messages related to the

JTAG chain, check your programming cable installation and board setup to ensure that it is set up

correctly.

After the script configures the FPGA, it downloads the compiled Nios II software to the board and

establishes a terminal connection with the board. The test software performs test sweeps on the SDRAM

by varying the following parameters:

• Pattern type

• Memory block size

• Memory block trail distance (number of blocks by which the pattern reader trails the pattern writer)

• Memory span tested

Ensure that you have only one set of generated system files in the project directory, otherwise the batch

script to program the device fails with an error from the software build tools.

The memory throughput values appear in the command terminal as the memory is tested. These values

are reported in hexadecimal and represent the number of clock cycles required to test the entire SDRAM

address span. The output is restricted to hexadecimal due to a small software library that prints the

characters to the terminal. Because the memory tester system writes to the memory and then reads it back,

the number of bytes it accesses and reports in the transcript window is double the memory span. This

number varies depending on the span of memory being tested for your memory device. Knowing the data

width of the memory interface, the number of bytes transferred, and the number of clock cycles for the

transfer, you can determine the memory access efficiency.

The SDRAM controller in the top-level Qsys system has a 32-bit local interface width, therefore memory

data width in bytes is 4 bytes for the tutorial design.

Efficiency = 100 × total bytes transferred/(memory data width in bytes × total

clock cycles)

The memory test runs until the design finishes testing the complete memory. To end the test early, type

Ctrl+C in the command window. To calculate the efficiency for the last throughput numbers in, convert

the hexadecimal numbers to decimal, as follows:

• 0x4000000 bytes transferred is 0d67108864 total bytes transferred

• 0x107d856 clock cycles is 0d17291350 total clock cycles

Therefore, the efficiency for this example is:

100 × 67108864 / (4 × 17291350) = 97.0%

TU-01006

2015.05.04

Compiling and Downloading Software to a Development Board

Qsys System Design Tutorial

Altera Corporation

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